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When the chips are down: beating the counterfeiters

28 August 2008

The financial cost to the industry of fake components and IP theft has been estimated at $2 to $3bn. Among various systems available to counter this criminal practice is a novel concept for chip tagging developed by an Edinburgh based company

Edinburgh based Algotronix has launched a novel concept in tagging to help counter the rapidly growing trade in stolen IP, counterfeit chips and cloned designs. DesignTag is a small, low-cost IP core that can be included in an FPGA design or built into a semiconductor. It allows ownership of the design to be positively established and helps in the fight against piracy and fraud.

The system comprises a digital core coded with a customer-specific ‘signature’ that can be identified externally from a working device without having to read the FPGA bit stream or de-encapsulate the chip. It works by modulating the power dissipation of the host device by around 5mW; this creates small temperature changes which are sensed by a thermocouple and decrypted by the reader software running on a PC. Ownership details are then simply extracted from the database.

With the rise of programmable logic it is now easier than ever to steal a design by copying the configuration bit stream. “The problem is how to deter theft and prove ownership of the design,” says Algotronix managing director, Tom Kean. “This is where DesignTag can help. The circuitry for DesignTag is buried withing the FPGA bit stream and is very difficult to locate and disable – even if the fraudster knows that it is included”.

The tag can also be used to confirm the design revision loaded into the FPGA or to signal internal status conditions, such as, when an overflow has occurred or a soft error was detected in memory. Signalling is achieved without interrupting the system operation and without having to access the package pins.

The version shipping today for use with FPGAs is called DesignTag Red, currently available at an introductory price of $200 per code license. DesignTag Reader Software is available separately at a cost of $800, and a starter kit - comprising an evaluation board and thermocouple data logger, together with the Reader Software and licenses for five codes - is shipping at $2,000. An ASIC/ASSP version of DesignTag will be available shortly; this is targeted at identifying re-branded semiconductors and will be able to uncover parts that have been fraudulently remarked to enhance their value.

DesignTag Red is included in the top-level design. A different version, covering the license enforcement needs of third party IP core and CAD tool suppliers, will follow shortly and is designated DesignTag Black. It also provides a mechanism for IP core vendors to obtain product version or status information from IP cores embedded in a larger design. In this application, the top-level designer is prevented from disabling or removing the tag by additional protection mechanisms.


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