FPGA based prototyping revisited – reducing time to prototyping
05 June 2017
Chip developers are facing ever-increasing verification requirements driven by growing hardware and software complexity.
Fast time to results is essential for them to ensure that projects can meet schedules. During the chip development flow, they demand to use the right tools for the right job at the right time, requiring a combination of formal, simulation, emulation, and FPGA prototyping as indicated in Figure 1.
Initially, when IP blocks and sub-systems are developed, formal verification and simulation are the main core engines. Later, hardware assisted techniques like emulation and FPGA based prototyping find their application. While simulation of gate-level timing and test aspects is often that last step prior to committing to tape-out, FPGA based prototyping enables software development at higher speed than emulation, which in exchange offers better visibility into the hardware than FPGA based prototyping. While studies show that 80 percent or more of all designs are prototyped in FPGA eventually, traditional prototyping comes at a significant cost and effort for bringing up the design in FPGA based prototyping architectures.
Key challenges include the re-modelling and re-mapping of ASIC memories into scarce FPGA resources, synchronisation of clocks for multiple ASIC domains on PCB boards and within FPGAs, partitioning of the design if it cannot fit into a single FPGA and validation that after all the changes made to the design it is actually still functionally identical to the design with which the process started. Consequently, the time to prototype classically could take multiple months. As indicated in Figure 1 by way of left pointing arrows, if both simulation and FPGA based prototyping are accelerated or made available earlier, the time to tape-out can be reduced and development of software on FPGA based prototyping can start earlier.
As part of its Verification Suite, Cadence recently introduced both new simulation and FPGA based prototyping engines. The next generation simulation engine Xcelium is the industry’s first production-ready third-generation simulator combining a multi-core engine architected for fast System-on-Chip (SoC) simulation with a single-core engine that has been refactored for fast IP simulation. The patented multi-core solution automatically analyses designs and selects optimal configuration for speed, providing on-average simulation speed-up of 3X for RTL, 5X for gate-level and 10X for design for test. The single-core engine is proven to run a comprehensive set of simulation use cases and provides on average 2X speed-up over the Incisive Enterprise Simulator.
The next generation FPGA based prototyping platform Protium S1 introduces a common compile flow with Palladium Z1 emulation, providing congruency and re-use of verification environments, reduces the time-to-prototyping from months to 1-2 weeks as chip designers don’t have to do RTL changes, can utilise automatic partitioning and memory compilation as well as a fully integrated FPGA place-and-route capabilities. Performance is scalable from 3 to 100MHz from fully automatic to fully manual implementation with an advanced black-box methodology. The key target users for FPGA based prototyping – software developers – can utilise advanced software debug capabilities including memory upload and download, force and release of signals and a SCE-MI based transaction interface.
Key to the accelerated time to prototype is the multi-fabric compiler as shown in Figure 2. Traditional FPGA based prototyping flows as indicated on the left hand side require significant changes of the RTL to fit the design into an FPGA fabric and to partition it across multiple FPGAs, followed by FPGA synthesis and partitioning and place & route (P&R). Each of the iterations can take multiple days and because of the changes made to the RTL, functional verification is a challenge, exacerbated by the challenge that visibility into FPGA based fabrics is much more limited than in processor based emulation.
In contrast, the Protium S1 flow is using the same front-end as emulation does. Memories are compiled automatically using a comprehensive library of memory models and clocking is taken care of automatically by synchronising all clocks in the design to a master “step-clock”. Users can guide the partitioning manually using their knowledge of the design, and use the full debug capabilities of Palladium Z1 emulation prior to committing to time consuming FPGA P&R. In addition, the front-end compile knowledge is forwarded as constraints to the FPGA P&R, optimising partitioning and making the layout much more predictable.
The resulting prototype – now available much earlier in the design flow than in traditional, older approaches, is optimised for software developers as indicated in Figure 3, which illustrates how a SoC with its software stack is mapped into Protium S1. Hardware debug is more limited than in emulation that has simulation like capabilities of being able to look at all signals in the design over a specific time period, but is more than respectable for initial debug tasks. Waveforms are aligned not per FPGA but across partitions, users can monitor signals easily and compile probes into the design in advance. A very unique capability is the ability to force and release signals in a design to allow “what if this 1 would be a 0” type of assessments.
Classic software debug with debuggers like Lauterbach T32 and ARM DS-5 is done via JTAG just as on the real chip and board later on, but with a lot more flexibility to allow scripting, clock control, start and stop as well as backdoor memory accesses to load memories with new tests or updated software versions to be booted.
With the combination of fast time to prototype from months to days using the multi-fabric compile flow with emulation and new unique features that are made available to software developers, Protium S1 literally allows users to revisit FPGA based prototyping and enable software development much earlier than in classic development flows.
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