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Stanford team combines logic, memory to build a 'high-rise' chip

15 December 2014

For decades, the mantra of electronics has been smaller, faster, cheaper. Now, Stanford engineers have added a fourth word - taller.

An illustration of the four-layer prototype. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic 'elevators' connecting logic and memory (Max Shulaker/Stanford

At a conference in San Francisco, a Stanford team will reveal how to build 'high-rise' chips that could leapfrog the performance of single-storey logic and memory chips that compute and store data. 

When a computer gets busy, the wires connecting logic and memory can get jammed. The Stanford approach would end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip.

Many thousands of nanoscale electronic 'elevators' would move data between the layers much faster, using less electricity, than the bottle-neck prone wires connecting today's single-storey logic and memory chips.

The work is led by Stanford' Professor Subhasish Mitra and Professor Philip Wong. They describe their new high-rise chip architecture in a paper to be presented at the IEEE International Electron Devices Meeting (IEDM) this week (December 15-17).

The innovation takes advantage of three breakthroughs. The first is a new technology for creating transistors; the second is a new type of computer memory that lends itself to multi-storey fabrication; the third is a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.

"This research is at an early stage, but our design and fabrication techniques are scalable," Mitra says. "With further development this architecture could lead to computing performance that is much, much greater than anything available today." The prototype chip unveiled at IEDM shows how to put logic and memory together into three-dimensional structures that can be mass-produced.

For the logic, the team created a dense layer of carbon nanotube transistors using a novel technique (growing them on a quartz substrate and subsequently transferring them to a silicon wafer), and for the memory they adopted new technology, unveiled at IEDM last year.

Unlike today's memory chips, this new storage technology is not based on silicon. Instead, the Stanford team fabricated memory using titanium nitride, hafnium oxide and platinum to form a metal/oxide/metal sandwich.

This structure can be made to change from a resistive to a conductive state (creating digital zeroes and ones). The technology is termed 'resistive random access memory' (RRAM). Wong's RRAM design uses less energy than current memory devices.

This new memory technology is also the key to creating the high-rise chip because RRAM can be made at much lower temperatures than silicon memory.

Stanford graduate students, Max Shulaker and Tony Wu created the fabrication techniques behind the four-storey prototype chip, which is unveiled this week at the conference.

The low-heat process for making RRAM and CNTs enabled them to fabricate each layer of memory directly atop each layer of CNT logic. And while making each memory layer, they were able to drill thousands of interconnections into the logic layer below. And it is this multiplicity of connections that enables the high-rise chip to avoid the data 'traffic jams' experienced with conventional wire interconnected circuits.




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